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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7172/adv7173 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 digital pal/ntsc video encoder with six dacs (10 bits), color control and enhanced power management features itu-r 1 bt601/656 ycrcb to pal/ntsc video encoder six high quality 10-bit video dacs ssaf? (super sub-alias filter) advanced power management features pc98-compliant (tv detect with polling and auto shutdown to save on power consumption) low power dac mode individual dac on/off control variable dac output current (5 maC36 ma) ultralow sleep mode current hue, brightness, contrast and saturation controls cgms (copy generation management system) wss (wide screen signalling) ntsc-m, pal-m/n, pal-b/d/g/h/i, pal-60 yuv betacam, mii and smpte/ebu n10 output levels single 27 mhz clock required ( 2 oversampling) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) component yuv euroscart rgb component yuv + chroma + luma + cvbs euroscart output rgb + chroma + luma + cvbs programmable clamping output signal advanced programmable power-on reset sequencing video input data port supports: ccir-656 4:2:2 8-bit parallel input format smpte 170m ntsc-compatible composite video itu-r bt.470 pal-compatible composite video luma sharpness control programmable luma filters (low-pass [pal/ntsc], notch [pal/ntsc], extended [ssaf], cif and qcif) programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz and 2.0 mhz], cif and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay ccir and square pixel operation integrated subca rrier locking to external video source color signal control/burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation macrovision antitaping rev 7.1 (ADV7172 only) 2 closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c ? -compatible and fast i 2 c) single supply 5 v or 3.3 v operation small 48-lead lqfp package applications high performance dvd playback systems, portable video equipment including digital still cameras and laptop pcs, video games, pc video/multimedia and digital satellite/cable systems (set-top boxes/ird) notes * this device is protected by u.s. patent numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. 1 itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). 2 the macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. ple ase contact sales office for latest macrovision version available. ssaf is a trademark of analog devices, inc. i 2 c is a registered trademark of philips corporation. general description the ADV7172/adv7173 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. there are six dacs available on the ADV7172/adv7173. in addition to the composite output signal there is the facility to output s-vhs y/c video, rgb video and yuv video. the on-board ssaf (super sub-alias filter), with extended luminance frequency response and sharp stopband attenuation, enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an additional sharpness control feature allows extra luminance boost on the frequency response. an advanced power management circuit enables optimal control of power consumption in both normal operating modes and power down or sleep modes. a pc98-compliant autodetect feature has been added to allow the user to determine whether or not the dacs are correctly terminated. if not, the ADV7172/ adv7173 flags that they are not connected through the status bit and provides the option of automatically powering them down, thereby reducing power consumption. the ADV7172/adv7173 also supports both pal and ntsc square pixel operation. the parts also incorporate wss and cgms-a data control generation.
rev. b ADV7172/adv7173 C2C functional block diagram 8 8 10-bit dac r set1 comp1 ADV7172/adv7173 color data p0 v ref r set2 comp2 p7 dac e dac f dac d dac a dac b dac c brightness and contrast control + add sync + interpolator 10 luma programmable filter + sharpness filter saturation control + add burst + interpolator 10 programmable chroma filter 10 8 8 8 real-time control circuit screset/rtc modulator + hue control 10 10 10 10 10-bit dac 10 10-bit dac 10 m u l t i p l e x e r y u v 8 4:2:2 to 4:4:4 inter- polator 10 10 sin/cos dds block dac control block dac control block 10-bit dac 10 10 10 10 10-bit dac 10 10-bit dac 10 m u l t i p l e x e r yuv to rbg matrix + yuv level control block i 2 c mpu port hsync field/ vsync blank ttx ttxreq v aa reset teletext insertion block ycrcb to yuv matrix clock cso_hso vso clamp sclock sdata alsb video timing generator gnd pal ntsc the ADV7172/adv7173 is designed with four color controls (hue, contrast, brightness and saturation). all yuv formats (smpte/ebu n10, mii and betacam) are supported in both pal and ntsc. the output video frames are synchronized with the incoming data timing reference codes. optionally the encoder accepts (and can genera te) hsync , vsync , and field timing s ignals. these timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. the encoder requires a single two times pixel rate (27 mhz) clock for standard opera- tion. alternatively the encoder requires a 24.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. hso/cso and vso ttl outputs, synchronous to the analog output video, are also available. a programmable clamp out- put signal is also available to enable clamping in either the front or back porch of the video signal. a separate teletext port enables the user to directly input teletext data during the vertical blanking interval. the ADV7172/adv7173 modes are set up over a 2-wire serial bidi rectional port (i 2 c-compatible) with two slave addresses. functionally the adv7173 and ADV7172 are the same with the exception that the ADV7172 can output the macrovision anti- copy algorithm. the ADV7172/adv7173 is packaged in a 48-lead lqfp pack- age (1.4 mm thickness). data path description for pal b, d, g, h, i, m, n, and ntsc m, n modes, ycrcb 4:2:2 data is input via the ccir-656-compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to form three data paths. y typically has a range of 16 to 235, cr, and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb, and cr. the ADV7172/ adv7173 supports pal (b, d, g, h, i, n, m) and ntsc (with and without pedestal) standards. the y data is then manipulated by being scaled for contrast control and a setup level is added for brightness control. the cr, cb data is also scaled and saturation control is added. the appropriate sync, blank and burst levels are then added to the ycrcb data. mac- rovision antitaping (ADV7172 only), closed-captioning and teletext levels are also added to y, and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is fil- tered and scaled by three digital fir filters. the u and v signals are modulated by the appropriate sub- carrier sine/cosine phases and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. the resulting u and v signals are then added together to make up the chrominance signal. the luma (y) signal can be delayed 1C3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to generate rgb data with appro- priate sync and blank levels. there are six dacs on the ADV7172/adv7173. three of these dacs are capable of providing 34.66 ma of current. the other three dacs provide 8.66 ma each. the six l0-bit dacs can be used to output: 1. composite video + rgb video + luma + chroma. 2. composite video + yuv video + luma + chroma. alternatively, each dac can be individually powered off if not required. a complete description of dac output configurations is given in appendix 8. video output levels are illustrated in appendix 6.
rev. b C3C ADV7172/adv7173 (v aa = 5 v 5% 1 , v ref = 1.235 v, r set1,2 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.) parameter test conditions 1 min typ max unit static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 3 1.0 lsb differential nonlinearity 3 guaranteed monotonic 1.0 lsb digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs output current (dacs a, b, c) 4 r set1 = 150 ? , r l = 37.5 ? 33 34.7 37 ma output current (dacs a, b, c) 5 r set1 = 1041 ? , r l = 262.5 ? 5ma output current (dacs d, e, f) 6 r set2 = 600 ? , r l = 150 ? 8.25 8.66 9.25 ma output current (dacs d, e, f) 5 r set2 = 1041 ? , r l = 262.5 ? 5ma dac-to-dac matching (dacs a, b, c) 7 1 4.0 % dac-to-dac matching (dacs d, e, f) 7 1 4.0 % output compliance, v oc 0 1.4 v output impedance, r out 30 k ? output capacitance, c out i out = 0 ma 30 pf voltage reference reference range, v ref i vrefout = 20 a 1.112 1.235 1.359 v power requirements v aa 4.75 5.0 5.25 v normal power mode i dac (max) 8, 9 r set1,2 = 600 ? 59 65 ma i dac (min) 8, 9 r set1,2 = 1041 ? 30 ma i cct 10 78 90 ma low power mode i dac (max) 11 r set1 = 150 ? 64 ma i dac (min) 11 15 ma i cct 10 78 90 ma sleep mode i dac 12 0.1 a i cct 13 0.1 a power supply rejection ratio comp = 0.1 f 0.01 0.5 %/% notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to 70 c. 3 characterized by design. 4 full drive into 75 ? doubly terminated load. 5 minimum drive current (used with buffered/scaled output load). 6 full drive into 150 ? load. 7 specification guaranteed by characterization. 8 i dac is the total current ( ?in?corresponds to 5 ma output per dac, ?ax?corresponds to 8.66 ma output per dac ) to drive dacs a, b, c, d, e, f. turning off individual dacs reduces i dac correspondingly, also dacs a, b, c can be configured to output a max current of 37 ma but dac d, e, f must be turned off. 9 all six dacs on (dac a, b, c, d, e, f). 10 i cct (circuit current) is the continuous current required to drive the device. 11 only large dacs (dacs a, b, c) on per low power mode. 12 total dac current in sleep mode. 13 total continuous current during sleep mode. specifications subject to change without notice. 5 v specifications specifications
rev. b C4C ADV7172/adv7173?pecifications parameter test conditions 1 min typ max unit static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 1.0 lsb differential nonlinearity guaranteed monotonic 1.0 lsb digital inputs 3 input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in v in = 0.4 v or 2.4 v 1 a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 a three-state output capacitance 10 pf analog outputs 3 output current (dacs a, b, c) 4 r set1 = 150 ? , r l = 37.5 ? 34.7 ma output current (dacs a, b, c) 5 r set1 = 1041 ? , r l = 262.5 ? 5ma output current (dacs d, e, f) 6 r set2 = 600 ? , r l = 150 ? 8.66 ma output current (dacs d, e, f) 5 r set2 = 1041 ? , r l = 262.5 ? 5ma dac-to-dac matching (dacs a, b, c) 3 1 4.0 % dac-to-dac matching (dacs d, e, f) 3 1 4.0 % output compliance, v oc 1.4 v output impedance, r out 30 k ? output capacitance, c out i out = 0 ma 30 pf power requirements 3, 7 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 8, 9 r set1,2 = 600 ? 58 65 ma i dac (min) 8 r set1,2 = 1041 ? 30 ma i cct 10 40 ma sleep mode i dac 11 0.1 a i cct 12 0.1 a power supply rejection ratio comp = 0.1 f 0.01 %/% notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : 0 c to 70 c. 3 guaranteed by characterization. 4 full drive into 75 ? doubly terminated load. 5 minimum drive current (used with buffered/scaled output load). 6 full drive into 150 ? load. 7 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 8 i dac is the total current ( ?in?corresponds to 5 ma output per dac, ?ax?corresponds to 8.66 ma output per dac ) to drive dacs a, b, c, d, e, f. turning off individual dacs reduces i dac correspondingly, also dacs a, b, c can be configured to output a max current of 37 ma. 9 dacs a, b, c can output 35 ma typically at 3.3 v (r set = 150 ? and r l = 37.5 ? ), optimum performance obtained at 18 ma dac current (r set = 300 ? and r l = 75 ? ). 10 i cct (circuit current) is the continuous current required to drive the device. 11 total dac current in sleep mode. 12 total continuous current during sleep mode. specifications subject to change without notice. 3.3 v specifications (v aa = 3.0 v?.6 v 1 , v ref = 1.235 v, r set1,2 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.)
rev. b C5C ADV7172/adv7173 parameter conditions 1 min typ max unit differential gain 3, 4 normal power mode 0.3 0.7 % differential phase 3, 4 normal power mode 0.4 0.7 degrees differential gain 3, 4 lower power mode 0.5 1.0 % differential phase 3, 4 lower power mode 2.0 3.0 degrees snr 3, 4 (pedestal) rms 75 db rms snr 3, 4 (pedestal) peak periodic 66 db p-p snr 3, 4 (ramp) rms 60 db rms snr 3, 4 (ramp) peak periodic 58 db p-p hue accuracy 3, 4 0.7 degrees color saturation accuracy 3, 4 0.9 % chroma nonlinear gain 3, 4 referenced to 40 ire 1.2 % chroma nonlinear phase 3, 4 0.3 0.5 degrees chroma/luma intermod 3, 4 0.2 0.4 % chroma/luma gain inequality 3, 4 1.0 % chroma/luma delay inequality 3, 4 0.5 ns luminance nonlinearity 3, 4 1.0 1.7 % chroma am noise 3, 4 79 82 db chroma pm noise 3, 4 79 80 db notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v range. 2 temperature range t min to t max : 0 c to 70 c. 3 these specifications are for the low-pass filter only and guaranteed by design. 4 guaranteed by characterization. specifications subject to change without notice. 5 v dynamic specifications (v aa = 5 v 5% 1 , v ref = 1.235 v, r set1,2 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.) parameter conditions 1 min typ max unit differential gain 3 normal power mode 0.6 % differential phase 3 normal power mode 0.5 degrees differential gain 3 lower power mode 1.0 % differential phase 3 lower power mode 0.5 degrees snr 3 (pedestal) rms 75 db rms snr 3 (pedestal) peak periodic 70 db p-p snr 3 (ramp) rms 60 db rms snr 3 (ramp) peak periodic 58 db p-p hue accuracy 3 1.0 degrees color saturation accuracy 3 1.0 % luminance nonlinearity 3 1.1 % chroma am noise 3 83 db chroma pm noise 3 79 db chroma nonlinear gain 3, 4 referenced to 40 ire 1.2 % chroma nonlinear phase 3, 4 0.3 degrees chroma/luma intermod 3, 4 0.2 % notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : 0 c to 70 c. 3 guaranteed by characterization. 4 these specifications are for the low-pass filter only and guaranteed by design. specifications subject to change without notice. 3.3 v dynamic specifications (v aa = 3.0 v?.6 v 1 , v ref = 1.235 v, r set1,2 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.)
rev. b ADV7172/adv7173 C6C 5 v timing specifications (v aa = 5 v 5% 1 , v ref = 1.235 v, r set1 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max unit mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 after this period the 1st clock is generated 0.6 s setup time (start condition), t 4 relevant for repeated start condition. 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 5, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 4.0 ns data hold time, t 12 5.0 ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 15 24 ns digital output hold time, t 14 10 ns pipeline delay, t 15 37 clock cycles teletext port 3, 7 digital output access time, t 16 20 ns data setup time, t 17 2ns data hold time, t 18 6ns reset control 3 reset low time 3ns notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to 70 c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p7Cp0 pixel controls: hsync , field/ vsync , blank, vso, cso_hso , clamp clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx specifications subject to change without notice.
rev. b ADV7172/adv7173 C7C 3.3 v timing specifications (v aa = 3.0 v?.6 v 1 , v ref = 1.235 v, r set1,2 = 600 . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max unit mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 s sclock low pulsewidth, t 2 1.3 s hold time (start condition), t 3 after this period the 1st clock is generated 0.6 s setup time (start condition), t 4 relevant for repeated start condition. 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 4, 5, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 4.0 ns data hold time, t 12 5ns control setup time, t 11 5ns control hold time, t 12 3ns digital output access time, t 13 20 ns digital output hold time, t 14 12 ns pipeline delay, t 15 37 clock cycles teletext port 3, 4, 7 digital output access time, t 16 23 ns data setup time, t 17 2ns data hold time, t 18 6ns reset control 3, 4 reset low time 3ns notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : 0 c to 70 c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p7Cp0 pixel controls: hsync , field/ vsync , blank, vso, cso_hso , clamp clock input: clock 7 teletext port consists of the following: teletext output: ttxreq teletext input: ttx specifications subject to change without notice.
rev. b ADV7172/adv7173 C8C t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata sclock figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync , field/ vsync , blank cb y cr y cb y hsync , field/ vsync , blank , cso_hso , vso , clamp t 13 t 14 control i/ps control o/ps figure 2. pixel and control data timing diagram t 16 t 17 ttxreq clock ttx 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles t 18 figure 3. teletext timing diagram dac average current consumption dac d, e, f: the average current consumed by each dac is the dac output current as determined by r set2 /v ref (see appendix 8). dac a, b, c: in normal power mode the average current consumed by each dac is the dac output current as determined by r set1 (see appendix 8). in low power mode the average current consumed by each dac is approximately h alf the dac output current as determined by r set1. consult an-551 for detailed information on ADV7172/adv7173 power management.
rev. b ADV7172/adv7173 C9C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7172/adv7173 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . gnd C 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . 150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . 260 c analog outputs to gnd 2 . . . . . . . . . . . gnd C 0.5 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. package thermal performance the 48-lead lqfp package is used for this device. the junc- tion-to-ambient ( ja ) thermal resistance in still air on a four layer pcb is 54.6 c/w. the junction-to-case thermal resistance ( jc ) is 16.7 c. to reduce power consumption when using this part the user is advised to run the part on a 3.3 v supply, turn off any unused dacs. however, if 5 v operation is required the user can en able low power mode by setting mr16 to a logic 1. another alter- native way to further reduce power is to use external buffers that dramatically reduce the dac currents, the current can be low- ered to as low as 5 ma (see an-551 and appendix 8 for more details) from a nominal value of 36 ma. the user must at all times stay below the maximum junction temperature of 110 c. the following equation shows how to calculate this junction temperature: j unction temperature = [ v aa ( i dac + i cct ) j a ] 70 c where i dac = 10 ma + (sum of the average currents consumed by each powered-on dac). pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) alsb hsync field/ vsync blank gnd v aa p0 p1 p2 p3 p4 p5 p6 p7 cso hso v aa gnd v aa sclock sdata r set2 ADV7172/adv7173 dac f comp1 dac a v aa dac b v aa gnd v aa dac c dac d v aa gnd dac e clock gnd v aa vso reset pal ntsc clamp ttxreq screset/rtc r set1 v ref comp2 gnd ttx ordering guide temperature package package model range description option ADV7172kst 0 c to 70 c plastic thin st-48 quad flatpack adv7173kst 0 c to 70 c plastic thin st-48 quad flatpack
rev. b ADV7172/adv7173 C10C pin function description mnemonic input/output function p7Cp0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7Cp0) p0 represents the lsb. clock i ttl clock input. requires a stable 27 mhz reference clock for standard operation. alter- natively, a 24.5454 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. hsync i/o hsync (modes 1 and 2) control signal. this pin may be configured to output (master mode) or as an input and accept (slave mode) sync signals. field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or as an input (slave mode) and accept these control signals. blank i/o video blanking control signal. the pixel inputs are ignored when this is logic level 0. this signal is optional. screset/rtc i this pin can be configured as an input by setting mr42 and mr41 of mode register 4. it can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin will reset the subcarrier phase to field 0. alternatively it may be configured as a real- time control (rtc) input. v ref i/o voltage reference input for dacs or voltage reference output (1.235 v). r set1 i a 150 ? resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals from dacs a, b, and c (the large dacs). r set2 i a 600 ? resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals from dacs d, e, and f (the small dacs). comp1 o compensation pin for dacs a, b, and c. connect a 0.1 f capacitor from comp to v aa . for optimum dynamic performance in low power mode, the value of the comp1 capacitor can be lowered to as low as 2.2 nf. comp2 o compen sation pin for dacs d, e, and f. co nnect a 0.1 f capacitor from comp to v aa . dac a o green/composite/y analog output. this dac is capable of providing 34.66 ma output. dac b o blue/s-video y/u analog output. this dac is capable of providing 34.66 ma output. dac c o red/s-video c/v analog output. this dac is capable of providing 34.66 ma output. dac d o green/composite/y analog output. this dac is capable of providing 8.66 ma output. dac e o blue/s-video y/u analog output. this dac is capable of providing 8.66 ma output. dac f o red/s-video c/v analog output. this dac is capable of providing 8.66 ma output. sclock i mpu port serial interface clock input. sdata i/o mpu port serial data input/output. clamp o ttl output signal to external circuitry to enable clamping of all video signals. pal_ntsc i input signal to select pal or ntsc mode of operation, pin set to logic 1 selects pal. vso o vso ttl output sync signal. cso_hso o dual function cso or hso ttl output sync signal. alsb i ttl address input. this signal sets up the lsb of the mpu address. reset i the input resets the on-chip timing generator and sets the ADV7172/adv7 173 into default mode. this is ntsc operation, timing slave mode 0, dacs a, b, and c powered off, dacs d, e, and f powered on, composite and s-video out. ttx i teletext data input pin. ttxreq o teletext data request output signal used to control teletext data transfer. v aa p power supply (3 v to 5 v). gnd g ground pin.
rev. b ADV7172/adv7173 C11C filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr04 0 0 0 0 1 1 1 mr03 0 0 1 1 0 0 1 mr02 0 1 0 1 0 1 0 low-pass (ntsc) low-pass (pal) notch (ntsc) notch (pal) extended (ssaf) cif qcif 0.091 0.15 0.015 0.095 0.051 0.018 monotonic 4.157 4.74 6.54 6.24 6.217 3.0 1.5 7.37 7.96 8.3 8.0 8.0 7.06 7.15 ?6 ?4 ?8 ?6 ?1 ?1 ?0 figure 4. luminance internal filter specifications filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr07 0 0 0 0 1 1 1 mr06 0 0 1 1 0 0 1 mr05 0 1 0 1 0 1 0 1.3mhz low pass 0.65mhz low pass 1.0mhz low pass 2.0mhz low pass reserved cif qcif 0.084 monotonic monotonic 0.0645 0.084 monotonic 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 45 58.5 49 40 45 50 figure 5. chrominance internal filter specifications frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 figure 6. ntsc low-pass luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 figure 7. pal low-pass luma filter internal filter response the y filter supports several different freq uency responses, including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenuation, a cif response and a qcif response. the uv filter sup ports several different frequency responses, including four lo w-pass responses, a cif response and a qcif response. t hese can be seen in figures 4 to 18. in extended mode there is the option of twelve responses in the range from C4 db to +4 db. the desired response can be chosen by the user by programming the correct value via the i 2 c. the variation of frequency responses can be seen in figures 19 to 21. ( continued from page 2)
rev. b ADV7172/adv7173 C12C frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 8. ntsc notch luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 9. pal notch luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 10. extended mode (ssaf) luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 11. cif luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 12. qcif luma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 13. 1.3 mhz low-pass chroma filter
rev. b ADV7172/adv7173 C13C frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 14. 0.65 mhz low-pass chroma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 15. 1.0 mhz low-pass chroma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 16. 2.0 mhz low-pass chroma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 17. cif chroma filter frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 figure 18. qcif chroma filter frequency mhz 6 12345 8 7 0 magnitude db 5 15 20 10 25 0 figure 19. extended mode luma filter with programmable gain, negative response
rev. b ADV7172/adv7173 C14C frequency mhz 4 0 6 12345 7 amplitude db 3 1 0 2 3 1 2 figure 20. extended mode luma filter with programmable gain, positive response frequency mhz 4 6 1 magnitude db 2345 2 6 8 10 12 0 2 4 figure 21. e xtended mode luma filter with program mable gain, combined response color bar generation the ADV7172/adv7173 can be configured to generate 100/ 7.5/75/7.5 color bars for ntsc or 100/0/75/0 color bars for pal. these are enabled by setting mr46 of mode register 4 to logic 1. square pixel mode the ADV7172/adv7173 can be used to operate in square p ixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accord- ingly for square pixel mode operation. color signal control the color information can be switched on and off the video output using bit mr44 of mode register 4. burst signal control the burst information can be switched on and off the video output using bit mr45 of mode register 4. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the v ertical blanking interval. color controls the ADV7172/adv7173 allows the user the advantage of control- ling the brightness, contrast, hue and saturation of the color. contrast control contrast adjustment is achieved by scaling the y input data by a factor programmed by the user into the contrast control register bits 5C0. this factor allows the data to be scaled between 75% and 125%. brightness control the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the y data in pal mode, ntsc mode without pedestal or ntsc mode with pedestal, in which case it is added directly onto the 7.5 ire pedestal already present. the level added is programmed by the user into the brightness control register (bits 4C0) and the user is capable of adding from 0 ire to a maximum of 14 ire in 32 (2 5 ) steps. because of different gains in the datapath for each mode, different values may need to be programmed to obtain the same ire setup level in each mode. maximum brightness is achieved when 31 is programmed into the brightness control register. table i illus- trates the maximum setup/brightness amplitudes available in the various modes. note that if a level of less than 7.5 ire is required on the y data in ntsc mode, then ntsc without pedestal must be the mode selected. table i. maximum brightness levels available brightness control mode register setup ntsc no pedestal 00011111 14 ire ntsc pedestal 00011111 13 ire pal 00011111 99 mv color saturation control color adjustment is achieved by scaling the cr and cb input data by a factor programmed by the user into the color control registers 1 and 2, bits 5C0. this factor allows the data to be scaled between 75% and 125%. hue control the hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the color burst is modified and hence the hue is shifted. hue adjustment is under the con- trol of the hue control register. the ADV7172/adv7173 provides a range of 22 change in increments of 0.17578125 .
rev. b ADV7172/adv7173 C15C yuv levels this functionality is under the control of mode register 5, bits 2C0. bit 0 (mr50) allows the ADV7172/adv7173 to output smpte lev els on the y output when configured in ntsc m ode, and betacam levels on the y output when configured in pal mode and vice-versa. video sync betacam 286 mv 714 mv smpte 300 mv 700 mv mii 300 mv 700 mv as the datapath is branched at the output of the filters, the luma signal relating to the cvbs or s-video y/c output is unaltered. only the y output of the yuv outputs is scaled. bits 2C1 (mr52Cmr51) allow uv levels to have a peak-peak amplitude of 700 mv or 1000 mv, or the default values of 934 mv in ntsc and 700 mv in pal. autodetect control the ADV7172/adv7173 provides the option of automatically powering down the dacs a, b and c if they are not correctly terminated (i.e., the 75 ? cable is not connected to the dac). the voltage at the output of dacs a and b are compared to a selected reference level. this reference voltage (mr64) will depend on whether the user terminates with 37.5 ? (75 ? con- nected on the dac end and 75 ? connected at tv end of cable, i.e., combined load of 37.5 ? ) or 75 ? . it cannot operate in a dac buffering configuration. there are two modes of auto- detect operation provided by the ADV7172/adv7173: (1) mode 0: the state of termination of the dac may be read by reading the status bits in mode register 6. mr67 status bit indicates whether or not the composite dac is terminated, mr66 status bit indicates whether or not the luma dac is terminated. the user may then decide whether or not to power down the dacs using mr15Cmr0. (2) mode 1: the state of the dacs may be read as in mode 0. if either of the dacs is unterminated, they are automatically powered down. if the luma dac, dac b is powered down then dac c, the chroma dac, will also be powered down. the state of termination of the dac is checked each frame to decide whether or not it is to be powered up or down. mode register 6, bits 3C2, indicates which mode of operation is used. note that mode register 1, bits 5-3, must be enabled (1) for autodetect functionality to work. (dacs a, b, c are enabled.) vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not have line sync or pre-/post- equalization pulses (see figures 24 to 25). this mode of opera tion is called partial blanking and is selected by setting mr32 to 1. it allows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in digitized incoming ycbcr data stream (e.g., wss data, cgms, vps etc.). alternatively the entire vbi may be blanked (no vbi data inserted) on these lines by setting mr32 to 0. subcarrier reset together with the screset/rtc pin and bits mr42 and mr41 of mode register 4, the ADV7172/adv7173 can be used in subcarrier reset mode. the subcarrier phase will reset to field 0 at the start of the following field when a low to high transition occurs on this input pin. real-time control together with the screset/rtc pin and bits mr42 and mr41 of mode register 4, the ADV7172/adv7173 can be used to lock to an external video source. the real-time control mode allows the ADV7172/adv7173 to automatically alter the subcarrier frequency to compensate for line length variation. when the part is connected to a device that outputs a digital data stream in the rtc format (such as a adv7185 video decoder, see figure 22), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. this digital data stream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. 00hex should be written into all four subcarrier frequency registers when using this mode. video timing description the ADV7172/a dv7173 is intended to interface to off-the- shelf mpeg1 and mpeg2 decoders. as a consequence, the ADV7172/adv7173 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. the ADV7172/adv7173 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. the ADV7172/adv7173 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required. in addition, the ADV7172/adv7173 supports a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. the ADV7172/adv7173 has four distinct master and four distinct slave timing configurations. timing control is estab- lished with the bidirectional sync , blank , and field/ vsync pins. timing mode register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other.
rev. b ADV7172/adv7173 C16C h/ltransition count start low 128 rtc time slot: 01 14 67 68 not used in ADV7172/adv7173 19 valid sample invalid sample fscpll increment 1 8/llc 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved 0 notes 1 f sc pll increment is 22 bits long, value loaded into ADV7172/adv7173 fsc dds register is f sc pll increment bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7172/adv7173. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset ADV7172/adv7173 s dds composite video e.g., vcr or cable hsync field/ vsync clock green/composite/y red/chroma/v blue/luma/u green/composite/y blue/luma/u red/chroma/v ADV7172/adv7173 p7 p0 screset/rtc video decoder adv7185 lcc1 gll p19-p12 figure 22. rtc timing and connections mode 0 (ccir?56): slave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7172/adv7173 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately bef ore and after each line during active picture and retrace. mode 0 is illustrated in figure 23. the hsync , field/ vsync , and blank (if not used) pins should be tied high during this mode. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y figure 23. timing mode 0 (slave mode)
rev. b ADV7172/adv7173 C17C mode 0 (ccir?56): master option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7172/adv7173 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin and the f bit is output on the field/ vsync pin. mode 0 is illustrated in figure 24 (ntsc) and figure 25 (pal). the h, v, and f transitions relative to the video waveform are illustrated in figure 26. 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f figure 24. timing mode 0 (ntsc master mode) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 25. timing mode 0 (pal master mode)
rev. b ADV7172/adv7173 C18C analog video h f v figure 26. timing mode 0 data transitions (master mode) mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode the ADV7172/adv7173 accepts horizontal sync and odd/ even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is dis- abled, the ADV7172/adv7173 automatically blanks all normally blank lines as per ccir-624. mode 1 is illustrated in figure 27 (ntsc) and figure 28 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 6 78 9 10 11 20 21 22 display display vertical blank odd field even field blank field hsync figure 27. timing mode 1 (ntsc)
rev. b ADV7172/adv7173 C19C 622 623 624 625 1 2 3 4 5 6 7 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 figure 28. timing mode 1 (pal) mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode the ADV7172/adv7173 can generate horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the ADV7172/adv7173 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the risin g clock edge following the timing signal transitions. mode 1 is illustrated in figure 27 (ntsc) and figure 28 (pal). figure 29 il lus- trates the hsync , blank , and field for an odd-or-even field transition relative to the pixel data. field pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr y hsync blank figure 29. timing mode 1 odd/even field transitions master/slave
rev. b ADV7172/adv7173 C20C mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode the ADV7172/adv7173 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7172/adv7173 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 30 (ntsc) and figure 31 (pal). 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank vsync figure 30. timing mode 2 (ntsc) 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank display 320 vsync figure 31. timing mode 2 (pal)
rev. b ADV7172/adv7173 C21C mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode the ADV7172/adv7173 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7172/adv7173 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 30 (ntsc) and figure 31 (pal). figure 32 illustrates the hsync , blank , and vsync for an even-to-odd field transition relative to the pixel data. figure 33 illustrates the hsync , blank , and vsync for an odd-to-even field transition relative to the pixel data. pal = 12 * clock/2 ntsc = 16 * clock/2 hsync vsync blank pixel data pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr y figure 32. timing mode 2 even-to-odd field transition master/slave pal = 864 * clock/2 ntsc = 858 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 hsync vsync blank pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 cb y cr y cb figure 33. timing mode 2 odd-to-even field transition master/slave
rev. b ADV7172/adv7173 C22C mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode the ADV7172/adv7173 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the ADV7172/adv7173 automatically blanks all normally blank lines as per ccir-624. mode 3 is illustrated in figure 34 (ntsc) and figure 35 (pal). 522 523 524 525 1 2 3 4 5 67 8 9 1011 202122 display display vertical blank odd field even field blank field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 even field display display vertical blank hsync odd field blank field hsync figure 34. timing mode 3 (ntsc) 622 623 624 625 1 2 3 4 5 6 7 21 22 23 display display vertical blank odd field even field blank field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 hsync blank field hsync figure 35. timing mode 3 (pal)
rev. b ADV7172/adv7173 C23C power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port such that the pixel inputs p7Cp0 are not selected. after reset, the ADV7172/ adv7173 is automatically set up to operate in ntsc/pal mode, depending on the pal_ntsc pin. the subcarrier frequency registers are automatically loaded with the correct values for pal or ntsc. all other registers, with the exception of mode registers 1 and 2, are set to 00h. mode register 1 is set to 07h. this is to ensure dacs d, e, and f are on after pow er-up. all bits of mode register 2 are set to 0, with the exception of bit 3 (i.e., mode register 2 reads 08h). bit mr23 of mode register 2 is set to logic 1. this enables the 7.5 ire pedestal. reset sequence when reset becomes active, the ADV7172/adv7173 reverts to the default output configuration. dacs a, b, c are off and dacs d, e, f are powered on and output composite, luma and chroma signals respectively. mode register 2, bit 6 (mr26), resets to 0. the ADV7172/adv7173 internal timing is under the control of the logic level on the ntsc_pal pin. when reset is released y, cr, cb values corresponding to a black screen are input to the ADV7172/adv7173. output timing signals are still suppressed at this stage. when the user requires valid data, mr26 is set to 1 to allow the valid pixel data to pass through the encoder. digital output timing signals become active and the encoder timing is now under the control of the timing registers. if, at this stage, the user wishes to select a video standard different from that on the ntsc_pal pin, mode register 2, bit 5 (mr25) is set (1) and the video standard required is selected by program ming mode r egister 0. figure 36 illustrates the reset sequence t iming. sleep mode if after reset the screset/rtc and ntsc_pal pins are both set to high, the part ADV7172/adv7173 will power-up in sleep mode to facilitate low power consumption before all registers have been initialized. if mode register 6, bit 0 (mr60) is then set to (1) sleep mode control passes to mode register 2, bit 7 (i.e., control via i 2 c). sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impos- sible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error, and results in very minor sch phase jumps at the start of the four or eight field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the ADV7172/adv7173 is con- figured in rtc mode (mr41 = 1 and mr42 = 1). under these conditions (unstable video) the subcarrier phase reset should be enabled (mr42 = 0 and mr41 = 1) but no reset applied. in this configuration the sch phase will never be reset, which that the output video will now track the unstable input video. the subcarrier phase reset when applied will reset the sch phase to field 0 at the start of the next field (e.g., subcarrier phase reset applied in field 5 (pal) on the start of the next field sch phase w ill be reset to field 0). xxxxxxx xxxxxxx xxxxxxx xxxxxxx digital timing signals suppressed black value black value with sync valid video valid video 0 1 timing active reset composite/y chroma mr26 pixel data valid digital timing 0 512 figure 36. reset sequence timing diagram
rev. b ADV7172/adv7173 C24C cso , hso , and vso outputs the ADV7172/adv7173 supports three timing signals, cso (composite sync signal), hso (horizontal sync signal) and vso (vertical sync signal). t hese output ttl signals are aligned with the analog video outputs. hso and cso are shared on pin 10. mode register 7, bit mr75 can be used to configure this out- put pin. see figure 37 for an example of these waveforms. clamp output the ADV7172/adv7173 has a programmable clamp ttl output signal. the clamp signal is programmable to the front and back porch. mode register 5, bit mr57 can be used to control the porch position. also the position of the clamp signal can be varied by 1C3 clock cycles in a positive and negative direction from the default position. mode register 5, bits mr56, mr55, and mr54 control this position. mr57 = 1 mr57 = 0 0h figure 38. clamp output timing mpu port description the ADV7172 and adv7173 support a 2-wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. two inputs serial data (sdata) and serial clock (sclock) carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7172 and adv7173 each have four possible slave addresses for b oth read and write operations. these are unique addresses for each device and are illustrated in figure 39 and figure 40. the lsb sets either a read or write operation. l ogic level 1 corresponds to a read operation while logic level 0 corresponds to a write operation. a1 is set by setting the alsb pin of the ADV7172/adv7173 to logic level 0 or logic level 1. when alsb is set to 0, there is greater bandwidth on the i 2 c lines, which allows high-speed data transfers on this bus. when alsb is set to 1, there is reduced input band- width on the i 2 c lines, which means that impulses of less than 50 ns w ill not pass into the i 2 c internal controller. this mode is recommended for noisy systems. address control set up by alsb read/write control 0 write 1 read 1 1 0 1 0 1 a1 x figure 39. ADV7172 slave address address control set up by alsb read/write control 0 write 1 read 0 1 0 1 0 1 a1 x figure 40. adv7173 slave address to control the various devices on the bus the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte means that the master will read information from the peripheral. vso hso cso output video 52512345678910 11-19 example: ntsc figure 37. cso , hso , vso timing diagram
rev. b ADV7172/adv7173 C25C the ADV7172/adv7173 acts as a standard slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting sub- address. the subaddresses auto increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. there is one excep- tion. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto increment function should then be used to increment and access subcarr ier frequency regi sters 1, 2 and 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of se quence with normal read and write operations, then these cause an immediate jump to the idle condition. during a given sclock high period, the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7172/adv7173 will not issue an acknowledge and will return to the idle condition. if, in autoincrement mode, the user exceeds the highest subaddress, the following action will be taken: 1. in read mode the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. a no-acknowledge condition is where the sdata line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7172/adv7173 and the part will return to the idle condition. figure 41 illustra tes an example of data transfer for a read sequence and the start and stop conditions. 1-7 8 9 1-7 8 9 1-7 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure 41. bus data transfer figure 42 shows bus write and read sequences. register accesses the mpu can write to or read from all of the registers of the ADV7172/adv7173 except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all communi- cations with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcar- rier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, ntsc pedestal control/pal teletext control registers, cgms/wss registers, contrast register, u- or v-scale registers, hue adjust register, brightness control register and sharpness control register in terms of its configuration. all registers can be read from as well as written to. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit a(m) figure 42. write and read sequences
rev. b ADV7172/adv7173 C26C subaddress register (sr7?r0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write opera- tion is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 43 shows the various operations under the control of the subaddress register. 0 should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address. sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written here sr7 sr4 ADV7172/73 subaddress register address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h ... ... ... 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh sr6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 sr5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 sr4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 sr3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 . . . 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 . . . 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 . . . 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mode register 0 mode register 1 mode register 2 mode register 3 mode register 4 mode register 5 mode register 6 mode register 7 reserved reserved timing register 0 timing register 1 sub carrier frequency register 0 sub carrier frequency register 1 sub carrier frequency register 2 sub carrier frequency register 3 sub carrier phase register closed captioning extended data byte 0 closed captioning extended data byte 1 closed captioning data byte 0 closed captioning data byte 1 ntsc pedestal/teletext control register 0 ntsc pedestal/teletext control register 1 ntsc pedestal/teletext control register 2 ntsc pedestal/teletext control register 3 cgms/wss 0 cgms/wss 1 cgms/wss 2 teletext request control register contrast control register u scale register v scale register hue adjust register brightness control register sharpness control register reserved .... .... .... .... macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] macrovision register [ADV7172 only] sr2 sr1 sr0 figure 43. subaddress register
rev. b ADV7172/adv7173 C27C mode register 0 mr0 (mr07?r00) (address (sr4?r0) = 00h) figure 44 shows the various operations under the control of mode register 0. mr0 bit description output video standard selection (mr01?r00) these bits are used to set up the encoder mode. the ADV7172/ adv7173 can be set up to output ntsc, pal (b, d, g, h, i), pal m or pal n standard video. luma filter select (mr02?r04) these bits specify which luma filter is to be selected. the filter selection is made independent of whether pal or ntsc is selected. chroma filter select (mr05?r07) these bits select the chroma filter. a low-pass filter can be selected with a choice of cutoff frequencies (0.65 mhz, 1.0 mhz, 1.3 mhz, or 2 mhz), along with a choice of cif or qcif filters. mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) figure 45 shows the various operations under the control of mode register 1. mr1 bit description dac control (mr15?r10) mr15Cmr10 bits can be used to power down the dacs. this can be used to reduce the power consumption of the ADV7172/ adv7173 if any of the dacs are not required in the application. low power mode control (mr16) this bit enables the lower power mode of the ADV7172/ adv7173. t his will reduce by approximately 50% the average supply current consumed by each large dac which is powered on. for each dac in low power mode, the relationship between r set1 /v ref and the output current is unchanged by this (see appendix 8). this bit is only relevant to the larger dacs, dacs a, b, and c. dacs d, e, and f are not affected by this low power mode. reserved (mr17) a logic 0 must be written to this bit. chroma filter select mr07 mr06 0 0 0 1.3mhz low-pass filter 0 0 1 0.65mhz low-pass filter 0 1 0 1.0mhz low-pass filter 0 1 1 2.0mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr05 mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 output video standard selection mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) 1 1 pal (n) luma filter select mr04 mr03 0 0 0 low-pass filter (ntsc) 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 0 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr02 figure 44. mode register 0 (mr0) mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 low power mode control 0 disable 1 enable mr16 mr14 dac a dac c control mr15 mr17 zero should be written to this bit 0 power-down 1 normal 0 power-down 1 normal dac b dac c control dac c dac c control mr13 0 power-down 1 normal dac e dac c control mr11 0 power-down 1 normal mr12 0 power-down 1 normal dac d dac c control dac f dac c control mr10 0 power-down 1 normal figure 45. mode register 1 (mr1)
rev. b ADV7172/adv7173 C28C mode register 2 mr2 (mr27?r20) (address (sr4?r0) = 02h) mode register 2 is an 8-bit-wide register. figure 46 shows the various operations under the control of mode register 2. mr2 bit description rgb/yuv control (mr20) this bit enables the output from the dacs to be set to yuv or rgb output video standard. large dacs control (mr21) this bit controls the output from dacs a, b, and c. when this bit is set to 1, composite, luma, and chroma signals are output from dacs a, b, and c (respectively). when this bit is set to 0, rgb or yuv may be output from these dacs. scart enable control (mr22) this bit is used to switch the dac outputs from scart to a euroscart configuration. a complete table of all dac output configurations is shown in table ii. pedestal control (mr23) this bit specifies whether a pede stal is to be generated on the ntsc composite video signal. this bit is invalid in the pal mode. square pixel control (mr24) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.54 mhz clock must be supplied. for pal, a 29.5 mhz clock must be supplied. standard i 2 c control (mr25) this bit controls the video standard used by the ADV7172/ adv7173. when this bit is set to 1, the video standard bits programmed in mode register 0, bits 0C1, indicate the video standard. when this bit is set to 0, the ADV7172/adv7173 is forced into the standard selected by the ntsc_pal pin. pixel data valid control (mr26) after reset, this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the dacs. the ADV7172/adv7173 will be set to master mode timing. when this bit is set to 1 by the user (via the i 2 c), pixel data passes to the pins and the encoder reverts to the timing mode defined by timing mode register 0. sleep mode control (mr27) when this bit is set (1), sleep mode is enabled. with this mode enabled the ADV7172/adv7173 power consumption is reduced to less than 20 a. the i 2 c registers can be written to and read from when the ADV7172/adv7173 is in sleep mode. if 0 is written to mr27 when the device is in sleep mode, the ADV7172/adv7173 will come out of sleep mode and resume normal operation. also, if the reset signal is applied during sleep mode, the ADV7172/adv7173 will come out of sleep mode and resume normal operation. this mode will only operate when mr60 is set to a logic 1; otherwise sleep mode is con- trolled by the pal_ntsc and screset/rtc pin. mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 sleep mode control 0 disable 1 enable mr27 standard i 2 c control 0 disable 1 enable mr25 pixel data valid control 0 disable 1 enable mr26 square pixel control 0 disable 1 enable mr24 scart enable control 0 disable 1 enable mr22 rgb/yuv control 0 rgb output 1 yuv output mr20 pedestal control 0 pedestal on 1 pedestal off mr23 large dacs control 0 rgb/yuv/comp 1 comp/luma/chroma mr21 figure 46. mode register 2 (mr2) table ii. dac output configuration matrix mr22 mr21 mr20 dac a dac b dac c dac d dac e dac f 0 0 0 g b r cvbs luma chroma 0 0 1 y u v cvbs luma chroma 0 1 0 cvbs luma chroma g b r 0 1 1 cvbs luma chroma y u v 1 0 0 cvbs b r g luma chroma 1 0 1 cvbs u v y luma chroma 1 1 0 cvbs luma chroma g b r 1 1 1 cvbs luma chroma y u v
rev. b ADV7172/adv7173 C29C mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr31 mr30 reserved for revision code vbi open 0 disable 1 enable mr32 ttxrq bit mode control 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr33 active video filter 0 enable 1 disable mr37 closed captioning field selection 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) mr36 mr35 figure 47. mode register 3 (mr3) mode register 3 mr3 (mr37?r30) (address (sr4?r0) = 03h) mode register 3 is an 8-bit-wide register. figure 47 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr31?r30) this bit is read-only and indicates the revision of the device. vbi_open (mr32) this bit determines whether or not data in the vertical blank- ing interval (vbi) is output to the analog outputs or blanked. vbi_open is available in all timing modes. also, if both blank input (tr03) and vbi_open are enabled, tr03 takes priority. teletext enable (mr33) this bit must be set to 1 to enable teletext data insertion on the ttx pin. ttxrq bit mode control (mr34) this bit enables switching of the teletext request signal from a continuous high signal (mr34 = 0) to a bit wise request signal (mr34 = 1). closed captioning field selection (mr36?r35) these bits control the fields that closed captioning data is dis- played on. closed captioning information can be displayed on an odd field, even field, or both fields. active video filter (mr37) this bit controls the filter mode applied outside the active video portion of the line. this filter ensures that the sync rise and fall times are always on spec regardless of which luma filter is selected.
rev. b ADV7172/adv7173 C30C mode register 4 mr4 (mr47?r40) (address (sr4?r0) = 04h) mode register 4 is a 8-bit wide register. figure 48 shows the various operations under the control of mode register 4. mr4 bit description vsync _3h (mr40) when this bit is enabled (1) in slave mode, it is possible to drive the vsync active low input for 2.5 lines in pal mode and 3 lines in ntsc mode. when this bit is enabled in master mode, the ADV7172/adv7173 outputs an active low vsync signal for 3 lines in ntsc mode and 2.5 lines in pal mode. genlock selection (mr42?r41) these bits control the genlock feature of the ADV7172/adv7173. setting mr41 to logic 0 disables the screset/rtc pin and allows the ADV7172/adv7173 to operate in normal mode. by setting mr41 to 1, one of two operations may be enabled: 1. if mr42 is set to 0, the screset/rtc pin is configured as a subcarrier reset input and the subcarrier phase will reset to field 0 whenever a low-to-high field transition is detected on the screset/rtc pin. 2. if mr42 is set to 1, the screset/rtc pin is configured as a real-time control input and the ADV7172/adv7173 can be used to lock to an external video source. active video line duration (mr43) this bit switches between two active video line durations. a 0 selects ccir rec 601 (720 pixels pal/ntsc) and a 1 selects itu-r.bt 470 analog standard for active video dura- tion (710 pixels ntsc, 702 pixels pal). chrominance control (mr44) this bit enables the color information to be switched on and off the video output. burst control (mr45) this bit enables the color burst information to be switched on and off the video output. color bar control (mr46) this bit can be used to generate and output an internal color bar test pattern. the color bar configuration is 100/7.5/75/7.5 for n tsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled, the ADV7172/adv7173 is config- ured in a master timing mode. the output pins vsync /field, hsync and blank are three-state during color bar mode. interlaced mode control (mr47) this bit is used to set up the output to interlaced or noninter- laced mode. mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 chrominance control 0 enable color 1 disable color mr44 color bar control 0 disable 1 enable mr46 vsync 3h 0 disable 1 enable mr40 interlaced mode control 0 interlaced 1 noninterlaced mr47 burst control 0 enable burst 1 disable burst mr45 active video line duration 0 720 pixels 1 710/702 pixels mr43 genlock selection x 0 disable genlock 0 1 enable subcarrier reset pin 1 1 enable rtc pin mr42 mr41 figure 48. mode register 4 (mr4)
rev. b ADV7172/adv7173 C31C mode register 5 mr5 (mr57?r50) (address (sr4-sr0) = 05h) mode register 5 is an 8-bit-wide register. figure 49 shows the various operations under the control of mode register 5. mr5 bit description y-level control (mr50) this bit controls the y output level on the ADV7172/adv7173. if this bit is set (0), the encoder outputs smpte levels when configured in pal mode and betacam levels when configured in ntsc mode. if this bit is set (1), the encoder outputs betacam levels when configured in pal mode and smpte levels when configured in ntsc mode. uv-levels control (mr52?r51) these bits control the u and v output levels on the ADV7172/ adv7173. it is possible to have uv levels with a peak-peak amplitude of either 700 mv (mr52 + mr51 = 01) or 1000 mv (mr52 + mr51 = 10) in ntsc and pal. it is also possible to have default values of 934 mv for ntsc and 700 mv for pal (mr52 + mr51 = 00). rgb sync (mr53) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. clamp delay (mr55?r54) these bits control the delay or advance of the clamp signal in the front or back porch of the ADV7172/ad v7173. it is p ossible to delay or advance the pulse by 0, 1, 2 or 3 clock cycles. clamp delay direction (mr56) this bit controls a positive or negative delay in the clamp signal. if this bit is set (1), the delay is negative. if it is not set (0), the delay is positive. clamp position (mr57) this bit controls the position of the clamp signal. if this bit is set (1), the clamp signal is located in the back porch posi- tion. if this bit is set to (0), the clamp signal is located in the front porch position. mr51 mr50 mr57 mr52 mr54 mr53 mr55 mr56 clamp delay direction 0 positive 1 negative mr56 clamp position 0 front porch 1 back porch mr57 clamp delay 0 0 no delay 011 pclk 102 pclk 113 pclk mr55 mr54 uv-levels control 0 0 default levels 0 1 700mv 1 0 1000mv 1 1 reserved mr52 mr51 rgb sync 0 disable 1 enable mr53 y-level control 0 disable 1 enable mr50 figure 49. mode register 5 (mr5)
rev. b ADV7172/adv7173 C32C mode register 6 mr6 (mr67?r60) (address (sr4?r0) = 06h) mode register 6 is an 8-bit-wide register. figure 50 shows the various operations under the control of mode register 6. mr6 bit description power-up sleep mode control (mr60) after reset this bit is set to 0, if both screset/rtc and ntsc_pal pins are tied high, the part will power-up in sleep mode (to facilitate low power consumption before the i 2 c is initialized). when this bit is set to 1 (via the i 2 c), sleep mode control passes to mode register 2, bit 7. reserved (mr61) a logic 0 must be written to this bit. luma autodetect control (mr62) this bit controls which mode of autodetect operation is being used on the luma dac (dac b) on the ADV7172/adv7173. if this bit is set (0), mode 0 is on; if this bit is set (1), then mode 1 is being used. composite autodetect control (mr63) this bit controls which mode of autodetect operation is being used on the composite dac (dac a) on the ADV7172/ adv7173. if this bit is set (0), mode 0 is on; if this bit is set (1), then mode 1 is being used. dac termination control (mr64) this bit controls the load termination resistance detected by the autodetect functionality. if this bit is set (0), the autodetect feature is used to determine if a 75 ? termination is present. if this bit is set to (1), the autodetect feature is used to indicate if a 150 ? termination is present. reserved (mr65) a logic 0 must be written to this bit. luma dac status bit (mr66) this bit is a read-only status bit for the autodetect feature of the ADV7172/adv7173 and may be read to check whether or not the composite dac is terminated. if this bit is set (1), there is no termination; if this bit is set (0), the composite dac is terminated. composite dac status bit (mr67) this bit is a read only status bit for the autodetect feature of the ADV7172/adv7173 and may be read to check whether or not the luma dac is terminated. if this bit is set (1), there is no termination. if this bit is set (0), the luma dac is terminated. mr61 mr60 mr67 mr62 mr64 mr63 mr65 mr66 composite dac status bit 0 not terminated 1 terminated mr67 dac termination control 01 mode 12 mode mr64 luma dac status bit 0 not terminated 1 terminated mr66 comp autodetect control 0 mode 0 1 mode 1 mr63 luma autodetect control 0 mode 0 1 mode 1 mr62 mr61 zero should be written to this bit power-up sleep mode control 0 enable 1 disable mr60 zero should be written to this bit mr65 figure 50. mode register 6 (mr6)
rev. b ADV7172/adv7173 C33C mode register 7 mr7 (mr77?r70) (address (sr4?r0) = 07h) mode register 7 is an 8-bit-wide register. figure 51 shows the various operations under the control of mode register 7. mr7 bit description color control enable (mr70) this bit is used to enable control of contrast and saturation of color. if this bit is set (1), color controls are enabled; if this bit is set (0), the color control features are disabled. luma saturation control (mr71) when this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 after scaling by the contrast control. this prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. when this bit is set (0), this control is disabled. hue adjust enable (mr72) this bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7172/adv7173. when this bit is set (1), the hue of the color is adjusted by the phase offset described in the hue control register. when this bit is set (0) hue adjustment is disabled. brightness enable control (mr73) this bit is used to enable brightness control on the ADV7172/ adv7173 by enabling the programmable setup level or ped- estal described in the brightness control register to be added to the scaled y data. when this bit is set (1), brightness control is enabled. when this bit is set (0), brightness control is disabled. sharpness response enable (mr74) this bit is used to enable the sharpness of the luminance signal on the ADV7172/adv7173 (mr04Cmr02 = 100). the various responses of the filter are determined by the sharpness re sponse register. when this bit is set (1) the luma response is altered by the amount described in the sharpness response register. when this bit is set (0), the sharpness control is disabled (see figures 19, 20, and 21 for luma signal responses). cso_hso output control (mr75) this bit is used to determine whether hso or cso ttl out- put signal is output at the cso_hso pin. if this bit is set (1), then the cso ttl signal is output. if this bit is set (0), then the hso ttl signal is output. reserved (mr77?r76) a logic 0 must be written to these bits. mr71 mr70 mr77 mr72 mr74 mr73 mr75 mr76 mr77 mr76 zero should be written to these bits cso_hso output control 0 hso out 1 cso out mr75 brightness enable control 0 disable 1 enable mr73 luma saturation control 0 disable 1 enable mr71 sharpness response enable 0 disable 1 enable mr74 hue adjust enable 0 disable 1 enable mr72 color control enable 0 disable 1 enable mr70 figure 51. mode register 7 (mr7)
rev. b ADV7172/adv7173 C34C timing register 0 (tr07?r00) (address (sr4?r0) = 0ah) figure 52 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr0 bit description master/slave control (tr00) this bit controls whether the ADV7172/adv7173 is in master or slave mode. timing mode selection (tr02?r01) these bits control the timing mode of the ADV7172/adv7173. these modes are described in more detail in the timing and control section of the data sheet. blank input control (tr03) this bit controls whether the blank input is used when the part is in slave mode or whether blank is internally generated. luma delay (tr05?r04) these bits control the addition of a delay to the luminance with respect to the chrominance. each bit represents a delay of 74 ns. min luma value (tr06) the bit is used to control the minimum luma value output by the ADV7172/adv7173. when this bit is set to (1), the luma is limited to 7.5 ire below the blank level. when this bit is set to (0), the luma value can be as low as the sync bottom level. timing register reset (tr07) toggling tr07 from low to high and low again resets the inter- nal timing counters. this bit should be toggled after power-up, reset or changed to a new timing mode. tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 blank input control 0 enable 1 disable tr03 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr05 tr04 timing mode selection 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 tr02 tr01 min luma value 0 luma min = sync bottom 1 luma min = blank 7.5 ire tr06 figure 52. timing register 0
rev. b ADV7172/adv7173 C35C timing register 1 (tr17?r10) (address (sr4?r0) = 0bh) timing register 1 is an 8-bit-wide register. figure 53 shows the various operations under the control of timing register 1. this register can be read from as well writ- ten to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr11?r10) these bits adjust the hsync pulsewidth. hsync to field/ vsync delay (tr13?r12) these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field rising edge delay (tr15?r14) when the ADV7172/adv7173 is in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. vsync width (tr15?r14) when the ADV7172/adv7173 is configured in timing mode 2, these bits adjust the vsync pulsewidth. hsync to pixel data adjust (tr17?r16) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustm ent is available in both master and slave timing modes. tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjust tr17 tr16 000 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to field/ vsync delay tr13 tr12 000 t pclk 014 t pclk 108 t pclk 1 1 16 t pclk t b hsync width 001 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 s tr15 tr14 t c vsync width (mode 2 only) 001 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) hsync field/ vsync t a t c tr15 tr14 figure 53. timing register 1
rev. b ADV7172/adv7173 C36C subcarrier frequency registers 3? (fsc3?sc0) (address (sr4?r0) = 0ch?fh) these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers is calculated by using the following equation: subcarrier frequency gister f f clk scf re = 2 32 C1 example: ntsc mode, f clk = 27 mhz, f scf = 3.5795454 mhz subcarrier frequencyvalue = 2 32 C . 1 27 10 3 579454 10 6 6 = 21 f 07 c 16 hex figure 54 shows how the frequency is set up by the four registers. subcarrier phase register (fp7?p0) (address (sr4?r0) = 10h) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 . for normal operation this register is set to 00hex. subcarrier frequency reg 3 subcarrier frequency reg 2 subcarrier frequency reg 1 subcarrier frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 figure 54. subcarrier frequency registers closed captioning even field data register 1? (ced15?ed0) (address (sr4?r0) = 11?2h) these 8-bit wide registers are used to set up the closed captioning extended data bytes on even fields. figure 55 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced0 ced7 ced2 ced14 ced13 ced11 ced9 ced12 ced8 ced15 ced10 figure 55. closed captioning extended data register closed captioning odd field data register 1? (ccd15?cd00) (subaddress (sr4?r0) = 13?4h) these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. figure 56 shows how the high and low bytes are set up in the registers. byte 1 ccd14 ccd13 ccd11 ccd9 ccd12 ccd8 ccd15 ccd10 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd0 ccd7 ccd2 figure 56. closed captioning data register ntsc pedestal/pal teletext control registers 3? (pce15?, pco15?)/(txe15?, txo15?) (subaddress (sr4?r0) = 15?8h) these 8-bit-wide registers are used to enable the ntsc pedes- tal/pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figures 57 and 58 show the f our control registers. a logic 1 in any of the bits of these registers has the effect of turn ing the pedestal off on the equivalent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. field 1/3 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco6 pco5 pco3 pco1 pco4 pco0 pco7 pco2 field 1/3 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 pco14 pco13 pco11 pco9 pco12 pco8 pco15 pco10 field 2/4 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce6 pce5 pce3 pce1 pce4 pce0 pce7 pce2 field 2/4 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 pce14 pce13 pce11 pce9 pce12 pce8 pce15 pce10 figure 57. pedestal control registers field 2/4 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe14 txe13 txe11 txe9 txe12 txe8 txe15 txe10 field 1/3 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo6 txo5 txo3 txo1 txo4 txo0 txo7 txo2 field 1/3 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txo14 txo13 txo11 txo9 txo12 txo8 txo15 txo10 field 2/4 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txe6 txe5 txe3 txe1 txe4 txe0 txe7 txe2 +
'* 0 1 2

rev. b ADV7172/adv7173 C37C teletext request control register tc07 (tc07?c00) (address (sr4?r0) = 1ch) teletext control register is an 8-bit-wide register. see figure 59. ttxreq rising edge control (tc07?c04) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. ttxreq falling edge control (tc03?c00) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increasing this value reduces the amount of teletext bits below the default of 360. if bits tc03Ctc00 are 00hex when bits tc07Ctc04 are changed, then the falling edge of ttxreq will track that of the rising edge (i.e., the time between the fall- ing and rising edge remains constant). cgms_wss register 0 c/w0 (c/w07?/w00) (address (sr4?r0) = 19h) cgms_wss register 0 is an 8-bit-wide register. figure 60 shows the operations under control of this register. c/w bit description cgms data (c/w03?/w00) these four data bits are the final four bits of cgms data out- put stream. note it is cgms data only in these bit positions i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, are calculated internally by the ADV7172/adv7173. if this bit is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd fields. note that this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even fields. note that this is only valid in ntsc mode. wide screen signal control (c/w07) when this bit is set (1), wide screen signalling is enabled. note that this is only valid in pal mode. tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk figure 59. teletext request control register cgms crc check control 0 disable 1 enable c/w04 wide screen signal control 0 disable 1 enable c/w07 c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 cgms odd field control 0 disable 1 enable c/w05 c/w03 c/w00 cgms data cgms even field control 0 disable 1 enable c/w06 figure 60. cgms_wss register 0
rev. b ADV7172/adv7173 C38C cgms_wss register 1 c/w1 (c/w17?/w10) (address (sr4?r0) = 1ah) cgms_wss register 1 is an 8-bit-wide register. figure 61 shows the operations under control of this register. c/w1 bit description cgms/wss data (c/w15?/w10) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. cgms data only (c/w17?/w16) these bits are cgms data bits only. cgms_wss register 2 c/w1(c/w27?/w20) (address (sr4-sr0) = 1bh) cgms_wss register 2 is an 8-bit-wide register. figure 62 shows the operations under control of this register. c/s bit description cgms/wss data (c/w27?/w20) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. contrast control register (cc07?c00) (address (sr4?r0) = 1dh) the contrast control register is an 8-bit-wide register used to scale the y output levels. figure 63 shows the operations under control of this register. cc0 bit description reserved (cc07?c06) a logic 0 must be written to these bits. y scalar value (cc05?c00) these six bits represent the value required to scale the y pixel data from 0.75 to 1.25 of its initial level. the value of these six bits is calculated using the following equation: contrast control register = ( x C0.785) 128 where x = scaling factor for y e.g., scale y by 0.9 contrast control register = (0.9C0.75) 128 = 19.2 = 010011 (rounded to the nearest integer) actual scaling factor = 0.898. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 c/w10 cgms/wss data c/w17 c/w16 cgms data figure 61. cgms_wss register 1 c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27 c/w20 cgms/wss data figure 62. cgms_wss register 2 cc07 cc06 cc05 cc04 cc03 cc02 cc01 cc00 cc05 cc00 y scalar value cc07 cc06 zero should be written to these bits figure 63. contrast control register
rev. b ADV7172/adv7173 C39C color control registers 2? (cc2?c1) (address (sr4?r0) = 1eh?fh) the color control registers are 8-bit-wide registers used to scale the u and v output levels. figure 64 shows the operations under control of these registers. cc1 bit description reserved (cc17?c16) a logic 0 must be written to these bits. u scalar value (cc15?c10) these six bits represent the value required to scale the u level from 0.75 to 1.25 of its initial level. the value of these six bits is calculated using the following equation: color control register 1 = ( x C 0.75) 128 where x = scaling factor for u e.g., scale u by 0.8 color control register 1 = (0.8 C 0.75) 128 = 6.4 = 000110 (rounded to the nearest integer) cc2 bit description reserved (cc27?c26) a logic 0 must be written to these bits. v scalar value (cc25?c20) these six bits represent the value required to scale the v pixel data from 0.75 to 1.25 of its initial level. the value of these six bits is calculated using the following equation: color control register 2 = ( x C 0.75) 128 where x = scaling factor for v e.g., scale v by 1.2 color control register 2 = (1.2 C 0.75) 128 = 57.6 = 111001 (rounded to the nearest integer) hue control register (hcr) (address (sr5?r0) = 20h) the hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. figure 65 shows the operation under control of this register. hcr bit description hue adjust value (hcr7?cr0) these eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier with respect to the phase of the subcarrier during the color burst. the ADV7172/adv7173 provides a range of 22 in incre- ments of 0.17578125 . for normal operation (zero adjustment) this register is set to 80 hex. ffhex and 00hex represent the upper and lower limit (respectively) of adjustment attainable. hue adjust = (0.17568125 [ hcr 7 C hcr 0 C 128]). cc17 cc16 cc15 cc14 cc13 cc12 cc11 cc10 cc15 cc10 u scalar value cc17 cc16 zero should be written to these bits cc27 cc26 cc25 cc24 cc23 cc22 cc21 cc20 cc25 cc20 v scalar value cc27 cc26 zero should be written to these bits figure 64. color control registers hcr7 hcr6 hcr5 hcr4 hcr3 hcr2 hcr1 hcr0 hcr7 hcr0 hue adjust value figure 65. hue control register
rev. b ADV7172/adv7173 C40C brightness control registers (bcr) (address (sr5?r0) = 21h) the brightness control register is an 8-bit-wide register which allows brightness control. figure 66 shows the operation under control of this register. bcr bit description reserved (bcr7?cr5) a logic 0 must be written to these bits. brightness value (bcr4?cr0) these five bits represent the value required to vary the brightness level or pedestal added to the luma data. the available range is from 0 ire to 7.5 ire in 18 steps. a value of 18 (10010) corre- sponds to 7.5 ire setup level added onto the pixel data. this brightness control is possible in both pal and ntsc. sharpness response register (pr) (address (sr5-sr0) = 22h) the sharpness response register is an 8-bit-wide register. the four msbs are set to 0. the four lsbs are written to in order to select a desired filter response. figure 67 shows the operation under control of this register. pr bit description reserved (pr7?r4) a logic 0 must be written to these bits. sharpness response value (pr3?r0) these four bits are used to select the desired luma filter response. the option of twelve responses is given supporting a gain boost/ attenuation in the range C4 db to +4 db. the value 12 (1100) written to these four bits corresponds to a boost of +4 db while the value 0 (0000) corresponds to C4 db. for normal o pera- tion these four bits are set to 6 (0110). refer to figures 19C21 for filter plots. bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 bcr4 bcr0 brightness value bcr7 bcr5 zero should be written to these bits figure 66. brightness control register pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 pr3 pr0 sharpness response value pr7 pr4 zero should be written to these bits figure 67. sharpness response register
rev. b ADV7172/adv7173 C41C the ADV7172/adv7173 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. the recommended analog circuit l ayout shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the ADV7172/ adv7173 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized to minimize induc- tive ringing. ground planes the ground plane should encompass all ADV7172/adv7173 ground pins, voltage reference circuitry, power supply bypass cir- cuitry for the ADV7172/adv7173, the analog output traces, and all the digital signal traces leading up to the ADV7172/adv 7173. the ground plane is the boards common ground plane. power planes the ADV7172/adv7173, and any associated analog circuitry, should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the ADV7172/adv7173. the metallization gap separating device power plane and board power plane should be as narrow as possible to mini- mize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all ADV7172/adv7173 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is appendix 1 board design and layout considerations obtained with 0.1 f ceramic capacitor decoupling. each group of v aa pins on the ADV7172/adv7173 must have at least one 0.1 f decoupling capacitor to gnd. these capacitors should be placed as close to the device as possible. it is important to note that while the ADV7172/adv7173 contains circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the ADV7172/adv7173 should be iso- lated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the ADV7172/adv7173 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not the analog power plane. analog signal interconnect the ADV7172/adv7173 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 ? load resistor connected to gnd. these resistors should be placed as close as possible to the ADV7172/adv7173 to minimize reflections. the ADV7172/adv7173 should have no inputs left floating. any inputs that are not required should be tied to ground.
rev. b ADV7172/adv7173 C42C 0.1 f 5v (v aa ) 23 comp2 35 33 4k 5v (v cc ) 150 21 4k 5v (v cc ) mpu bus 48 44 14 16 15 12, 13, 18, 26, 31, 47 17 20 38 1, 11, 19, 27, 30, 32, 34, 46 0.1 f 0.01 f 5v (v aa ) 10k 5v (v aa ) power supply decoupling for each power supply group 37 gnd alsb hsync field/ vsync blank reset clock r set1 sdata sclock dac a v aa v ref p0 p7 75 75 39 screset/rtc ADV7172/ adv7173 unused inputs should be grounded dac b 100 100 5v (v aa ) reset 41 ttx ttxreq 10k 5v (v aa ) ttx ttxreq 0.1 f 36 comp1 43 42 vso clamp pal_ntsc 29 28 dac c 75 300 dac d 25 24 dac e 300 dac f 600 22 r set2 9 2 10 300 45 40 27mhz clock (same clock as used by mpeg2 decoder) cso_hso 4k 4.7 f figure 68. recommended analog circuit layout
rev. b ADV7172/adv7173 C43C the ADV7172/adv7173 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two d ata bits and is followed by a logic level 1 start bit. sixteen b its of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the ADV7172/adv7173 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals, and timing to support closed capt ion- ing on lines 21 and 284, are automatically generated by the ADV7172/adv7173. all pixels inputs are ignored during lines 21 and 284. closed captioning is enabled. appendix 2 closed captioning 12.91 s s t a r t p a r i t y p a r i t y d0 d6 d0 d6 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 figure 69. closed captioning waveform (ntsc) fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the ADV7172/adv7173 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which will in turn load the new data (two bytes) every fie ld. if no new data is required for transmission, zeros must be inserted in both data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21, or a tv will not recognize them. if there is a message like hello world, which has an odd number of char- acters, it is important to pad it out to an even number to get end of caption 2-byte control code to land in the same field.
rev. b ADV7172/adv7173 C44C the ADV7172/adv7173 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the ADV7172/adv7173 is configured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a refer - ence pulse of the same amplitude and duration as a cgms bit (see figure 70). these bits are output from the configuration regis ters in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c 12, c/w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic 1, the last six bits, c19Cc14, which comprise the 6-bit crc check sequence, are calcul ated automatically on the ADV7172/adv7173 based on the lower 14 bits (c0Cc 13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0Cc19) are directly output from the cgms registers (no crc calculated, must be calculated by the user) . function of cgms bits word 0 C 6 bits word 1 C 4 bits word 2 C 6 bits crc C 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 undefined word 0 b4, b5, b6 identification information about video and other signals (e.g., audio) word 1 b7, b8, b9, b10 identification signal incidental to word 0 word 2 b11, b12, b13, b14 identification signal and information incidental to word 0 appendix 3 copy generation management system (cgms) crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire 40 ire figure 70. cgms waveform diagram
rev. b ADV7172/adv7173 C45C appendix 4 wide screen signaling the ADV7172/adv7173 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the ADV7172/adv7173 is configured in pal mode. the wss data is 14 bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 71 ). the bits are output from the configuration registers in the following order: c/w20 = w0, c/w21 = w1, c/ w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a logic 1 it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 s from the falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0Cbit 2 aspect ratio/format/position bit 3 is odd parity check of bit 0Cbit 2 b0 b1 b2 b3 aspect ratio format position 0001 4:3 f ull format nonapplicable 1000 14:9 letterbox center 0100 14:9 letterbox top 1101 16:9 letterbox center 0010 16:9 letterbox top 1011 >16:9 letterbox center 0111 14:9 f ull format center 1110 16:9 n onapplicable nonapplicable 11.0 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s figure 71. wss waveform diagram b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved
rev. b ADV7172/adv7173 C46C appendix 5 teletext insertion time, t pd, is the time needed by the ADV7172/adv7173 to interpolate input data on ttx and insert it onto the cvbs or y out- puts, such that it appears t synttxout = 10.2 s after the leading edge of the horizontal signal. time, ttx del , is the pipeline delay time by the source that is gated by the ttxreq signal in order to deliver ttx data. with the programmability offered with ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 s after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays. the width of the ttxreq signal must always be maintained such that it allows the insertion of 360 (in order to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mbits/s. this is achieved by setting tc03Ctc00 to 0. the insertion window is not open if the teletext enable (mr33) is set to 0. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is given as follows: (27 mhz/4) = 6.75 mhz (6.9375 10 6 /6.75 10 6 ) = 1.027777 thus 37 ttx bits correspond to 144 clocks (27 mhz) and each bit has a width of almost four clock cycles. the ADV7172/adv7173 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be outputted on the cvbs and y outputs. at the ttx input the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bi ts 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. after 37 ttx bits, the next bits with th ree clock cycles are 47, 56, 65, and 74. this scheme holds for all following cycles of 37 ttx bits, until all 360 ttx bits are completed. all teletext lines are implemented in the same way. individual control of teletext lines is controlled by teletext setup registers. address & data run-in clock teletext vbi line 45 bytes (360 bits) pal figure 72. teletext vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t synttxout = 10.2 s t pd = pipeline delay through ADV7172/adv7173 ttx del = ttxreq to ttx (programmable range = 4 bits [0 15 clock cycles]) t synttxout 10.2 s ttx del ttx st figure 73. teletext functionality diagram
rev. b ADV7172/adv7173 C47C appendix 6 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire 40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 74. ntsc composite video levels 100 ire 7.5 ire 0 ire 40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 75. ntsc luma video levels 650mv 335.2mv 963.8mv 0mv peak chroma blank/black level 286mv (p-p) 629.7mv (p-p) peak chroma figure 76. ntsc chroma video levels 100 ire 7.5 ire 0 ire 40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 77. ntsc rgb video levels
rev. b ADV7172/adv7173 C48C ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire 40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 78. ntsc composite video levels 100 ire 0 ire 40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv figure 79. ntsc luma video levels 650mv 299.3mv 978mv 0mv peak chroma blank/black level 286mv (p-p) peak chroma 694.9mv (p-p) figure 80. ntsc chroma video levels 100 ire 0 ire 40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv figure 81. ntsc rgb video levels
rev. b ADV7172/adv7173 C49C pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv figure 82. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv figure 83. pal luma video levels 650mv 317.2mv 989.7mv 0mv peak chroma blank/black level 300mv (p-p) 672mv (p-p) peak chroma figure 84. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv figure 85. pal rgb video levels
rev. b ADV7172/adv7173 C50C betacam level 0mv 171mv 334mv 505mv 0mv 171mv 334mv 505mv white yellow cyan green magenta red blue black figure 86. ntsc 100% color bars, no pedestal u levels betacam level 0mv 158mv 309mv 467mv 0mv 158mv 309mv 467mv white yellow cyan green magenta red blue black figure 87. ntsc 100% color bars with pedestal u levels smpte level 0mv 118mv 232mv 350mv 0mv 118mv 232mv 350mv white yellow cyan green magenta red blue black figure 88. pal 100% color bars, u levels uv waveforms betacam level 0mv 82mv 423mv 505mv 0mv 82mv 505mv 423mv white yellow cyan green magenta red blue black figure 89. ntsc 100% color bars, no pedestal v levels betacam level 0mv 76mv 391mv 467mv 0mv 76mv 467mv 391mv white yellow cyan green magenta red blue black figure 90. ntsc 100% color bars with pedestal v levels smpte level 0mv 57mv 293mv 350mv 0mv 57mv 350mv 293mv white yellow cyan green magenta red blue black figure 91. pal 100% color bars, v levels
rev. b ADV7172/adv7173 C51C if an output filter is required for the cvbs, y, uv, chroma and rgb outputs of the ADV7172/adv7173, the filter shown below can be used. the plot of the filter characteristics is shown in fig ure 93. an output filter is not required if the outputs of the ADV7172/adv7173 are connected to most analog monitors or analog tvs; however, if the output signals are applied to a system where sampling is used (e.g., digital tvs), then a filter is required to prevent aliasing. 1.8 h 22pf 270pf 330pf filter i/p filter o/p 75 figure 92. output filter used with output buffer appendix 7 optional output filter frequency hz 0 40 80 100m 10m 100k magnutude db 10 20 30 50 60 70 1m figure 93. output filter plot appendix 8 optional dac buffering when external buffering is needed of the ADV7172/adv7173 dac outputs, the configuration in figure 94 is recommended. this configuration shows the dac outputs, a, b, c, running at half (18 ma) their full current (36 ma) capability. this will allow the ADV7172/adv7173 to dissipate less power; the analog current is reduced by 50% with a r set1 = 300 ? and r set2 = 600 ? and an r load of 75 ? . this mode is recomm ended for 3.3 v operation as optimum performance is obtained from the ADV7172/adv7173 v ref pixel port v aa output buffer dac a cvbs chroma g luma b r 300 r set1 output buffer dac b output buffer dac c output buffer dac d output buffer dac e output buffer dac f digital core 600 r set2 figure 94. output dac buffering configuration dac outputs at 18 ma with a v aa of 3.3 v. this buffer also adds extra isolation on the video outputs (see buffer circuit in figure 95). note that dacs d, e, and f will always require buffering as the full-scale o utput current from these dacs is lim ited to 8.66 ma. with dacs a, b, and c, buffering is optional, based on the user requirements for performance and power consumption. when calculating absolute output full-scale current and voltage, use the following equations: v out = i out r load i out = v ref k () r set k = 4.2146 constant , v ref = 1.235 v ad8051 v cc + v cc 1 5 4 3 2 output to tv monitor input/ optional filter o/p figure 95. recommended output dac buffer
rev. b ADV7172/adv7173 C52C appendix 9 recommended register values the ADV7172/adv7173 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case the output is set to composite/luma/chroma outputs with dacs d, e and f powered up to provide 8.66 ma and with the blank input control disabled. additionally, the burst and color information are enabled on the output and the inter- nal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02Ctr00 of the timing register 0 control the timing modes. for a detailed explanation of each bit in the command registers, please turn to the register programming section of the data sheet. tr07 should be toggled after setting up a new timing mode. tim ing register 1 provides additional control over the position and duration of the timing signals. in the examples this register is programmed in default mode. ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 10hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal b, d, g, h, i (f sc = 4.43361875 mhz) address data 00hex mode register 0 11hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 01hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 a3hex 0dhex subcarrier frequency register 1 efhex 0ehex subcarrier frequency register 2 e6hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex
rev. b ADV7172/adv7173 C53C pal m (continued) (f sc = 3.57561149 mhz) address data 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 13hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal-60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex
rev. b ADV7172/adv7173 C54C power on reset reg values (pal_ntsc = 0, ntsc selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 00hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex power on reset reg values (pal_ntsc = 1, pal selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 00hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex
rev. b ADV7172/adv7173 C55C appendix 10 optional dac buffering 0.6 0.4 0.2 0.0 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00 db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 3 4 volts figure 96. 100/0/75/0 pal color bars microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts figure 97. 100/0/75/0 pal color bars luminance
rev. b ADV7172/adv7173 C56C apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal figure 98. 100/0/75/0 pal color bars chrominance apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.5 0.0 50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 figure 99. 100/7.5/75/7.5 ntsc color bars
rev. b ADV7172/adv7173 C57C noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 0.2 50.0 0.0 ire:flt volts f2 l238 figure 100. 100/7.5/75/7.5 ntsc color bars luminance noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 0.2 0.4 volts 50.0 50.0 f1 l76 ire:flt figure 101. 100/7.5/75/7.5 ntsc color bars chrominance
rev. b ADV7172/adv7173 C58C apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain 1.000 0.000db 625 line pal burst from source display +v & v figure 102. pal vector plot apl = 45.1% setup 7.5% r-y b-y yi g cy m g cy i r 75% 100% b b system line l76f1 angle (deg) 0.0 gain 1.000 0.000db 525 line ntsc burst from source q q i figure 103. ntsc vector plot
rev. b ADV7172/adv7173 C59C outline dimensions dimensions shown in inches and (mm). 48-lead lqfp (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09)
C60C c00222aC0C4/01(b) printed in u.s.a.

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